## Combinational Circuit MCQ

Combinational Circuit MCQ, Multiple Choice Questions on Combinational Circuit, Objective Questions on Combinational Circuit, Digital Electronics MCQ, Full Adder MCQ, Multiplexer MCQ, Demultiplexer MCQ, Encoder MCQ, Decoder MCQ, Engineering MCQ, Combinational Circuit MCQ, Combinational Logic Circuit MCQ

### Objective Type Questions

Q.1. The difference output in a full-subtractor is the same as the

- difference output of a half-subtractor
- sum output of a half-adder
- sum output of a full-adder
- carry output of a full-adder

**Answer: **sum output of a full-adder

Q.2. Which of the following logic circuits accepts two binary digits on inputs, and produces two binary digits, a sum bit and a carry bit on its outputs?

- full-adder
- half-adder
- serial adder
- parallel adder

**Answer:** half-adder

Q.3. How many inputs and outputs does a full-adder have?

- two inputs, two outputs
- two inputs, one output
- three inputs, two outputs
- two inputs, three outputs

**Answer:** three inputs, two outputs

Q.4. How many inputs and outputs does a full-subtractor circuit have?

- two inputs, one output
- two inputs, two outputs
- two inputs, three outputs
- three inputs, two outputs

**Answer:** three inputs, two outputs

Q.5. A full-adder can be realized using

- one half-adder, two OR gates
- two half-adders, one OR gate
- two half-adders, two OR gates
- two half-adders, one AND gate

**Answer:** two half-adders, one OR gate

Q.6. The minimum number of 2-input NAND/NOR gates required to realize a half-adder is

- 3
- 4
- 5
- 6

**Answer:** 5

Q.7. The minimum number of 2-input NAND/NOR gates required to realize a half-subtractor is

- 3
- 4
- 5
- 6

**Answer:** 5

Q.8. The minimum number of 2-input NAND gates required to realize a full-adder/full-subtractor is

- 8
- 9
- 10
- 12

**Answer:** 9

Q.9. The minimum number of 2-input NOR gates required to realize a full-subtractor is

- 8
- 9
- 10
- 12

**Answer:** 12

Q.10. How many full-adders are required to construct an *m*-bit parallel adder?

*m*/2*m*-1*m**m*+ 1

**Answer:*** m*-1

Q.11. Parallel adders are

- combinational logic circuits
- sequential logic circuits
- both of the above
- none of the above

**Answer:** combinational logic circuits

Q.12. In which of the following adder circuits is the carry ripple delay eliminated?

- half-adder
- full-adder adder
- parallel adder
- carry-look-ahead adder

**Answer:** carry-look-ahead adder

Q.13. To secure a higher speed of addition, which of the following is the preferred solution?

- serial adder
- parallel adder
- adder with a look-ahead-carry
- full-adder

**Answer:** adder with a look-ahead-carry

Q.14. A parallel adder in which the carry-out of each full-adder is the carry-in to the next significant digit adder is called a

- ripple carry adder
- look-ahead-carry adder
- serial carry adder
- parallel carry adder

**Answer:** ripple carry adder

Q.15. The adder preferred for applications where circuit minimization is more important than speed is

- parallel adder
- serial adder
- full-adder
- half-adder

**Answer:** serial adder

Q.16. A serial adder requires only one

- half-adder
- full-adder
- counter
- multiplexer

**Answer:** full-adder

Q.17. In digital systems, subtraction is performed

- using half-adders
- using half-subtractors
- using adders with l’s complement representation of negative numbers
- by none of the above

**Answer:** using adders with l’s complement representation of negative numbers

Q.18. In a digital system, BCD arithmetic is preferred to normal binary arithmetic because

- BCD arithmetic circuits are simpler than binary arithmetic circuits
- BCD arithmetic circuits are faster than binary arithmetic circuits
- BCD arithmetic circuits are less expensive than binary arithmetic circuits
- of ease of operation when input is in BCD format and the output display is decimal

**Answer:** of ease of operation when input is in BCD format and the output display is decimal

Q.19. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if

- the sum of two BCD numbers is not a valid BCD number
- the suns of two BCD numbers is not a valid BCD number or a carry is produced
- a carry is produced
- none of the above is true

**Answer:** the suns of two BCD numbers is not a valid BCD number or a carry is produced

Q.20. BCD subtraction is performed by using

- 1’s complement representation
- 2’s complement representation
- 5’s complement representation
- 9’s complement representation

**Answer:** 9’s complement representation

Q.21. Which logic gate is a basic comparator?

- NOR gate
- NAND gate
- X-OR gate
- X-NOR gate

**Answer:** X-NOR gate

Q.22. The logic gate used in parity checkers is

- NAND gate
- NOR gate
- X-OR gate
- X-NOR gate

**Answer:** X-OR gate

Q.23. A device whose inputs are decimal digits and/or alphabetic characters and whose outputs are the coded representations of those inputs is called

- an encoder
- a decoder
- a code convener
- a decimal converter

**Answer:** an encoder

Q.24. A logic circuit that responds to just one input, in accordance with some priority system, among those that may be simultaneously high is called

- an encoder
- a priority encoder
- a priority decoder
- a decoder

**Answer:** a priority encoder

Q.25. In the hexadecimal to binary priority encoder

- 0 (hex) has the highest priority
- 7 (hex) has the lowest priority
- F (hex) has the lowest priority
- F (hex) has the highest priority

**Answer:** F (hex) has the highest priority

Q.26. Selection of the input with the higher priority by an encoder is called

- arbitration
- input selection
- priority selection
- none of these

**Answer:** arbitration

Q.27. A logic circuit that converts an n-input binary code into a corresponding single numeric output is called

- an encoder
- a decoder
- a code converter
- a converter

**Answer:** a decoder

Q.28. A binary-to-octal decoder is

- 3-line to 8-line decoder
- 1-line to 8-line decoder
- 4-line to 8-line decode
- any lines-to-8 line decoder

**Answer:** 3-line to 8-line decoder

Q.29. A BCD-to-decimal decoder is

- a 3-line to 8-line decoder
- a 1-line to 10-line decoder
- a 4-line to 10-line decoder
- any lines to 10-lines decode

**Answer:** a 4-line to 10-line decoder

Q.30. The number of 3-line-to-8-line decoders required for selecting 1 out of 64 is

- 4
- 8
- 9
- 16

**Answer:** 9

Q.31. The number of 4-line-to-16-line decoders required to make an 8-line-to-256-line decoder is

- 16
- 17
- 32
- 64

**Answer:** 17

Q.32. A logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output is called

- a multiplexer
- a demultiplexer
- a transmitter
- a receiver

**Answer:** a multiplexer

Q.33. A multiplexer is also known as

- a data accumulator
- a data restorer
- a data selector
- a data distributor

**Answer:** a data selector

Q.34. How many select lines are contained in a multiplexer with 1024 inputs and one output?

- 512
- 258
- 64
- 10

**Answer:** 10

Q.35. What is the largest number of data inputs which a data selector with two control inputs can handle?

- 2
- 4
- 8
- 16

**Answer:** 4

Q.36. A multiplexer with four select bits is a

- 4:1 multiplexer
- 8:1 multiplexer
- 16: 1 multiplexer
- 32:1 multiplexer

**Answer:** 16: 1 multiplexer

Q.37. The number of select lines *m*, required to select one out of *n* input lines is

*m*= log_{2}*n**m*= log*n**m*= ln*n**m*= 2^{n }

**Answer:*** m* = log_{2} *n*

Q.38. A MUX with its address bits generated by a counter operates as a

- parallel-to-serial converter
- serial-to-parallel converter
- modified counter
- modified multiplexer

**Answer:** parallel-to-serial converter

Q.39. A 32:1 mux can be designed using

- two 16:1 muxs and one two input OR gate
- two 16:1 muxs and one two input AND gate
- two 16:1 muxs and two two-input OR gates
- two 16:1 muxs only

**Answer:** two 16:1 muxs and one two input OR gate

Q.40. The number of 16:1 multiplexers required for designing a 4-output 4-variable combinational circuit is

- 16
- 8
- 4
- 1

**Answer:** 4

Q.41. A 4-variable logic circuit can be designed using

- a 16:1 multiplexer
- an 8:1 multiplexer and one inverter
- two 8:1 multiplexers and one 2:1 multiplexer
- any of the above

**Answer:** any of the above

Q.42. A 16:1 multiplexer can be used to design

- 4 variable logic function
- BCD to binary code convener
- BCD to 7 segment decoder
- full-adder

**Answer:** 4 variable logic function

Q.43. A BCD to XS-3 code converter can be designed using

- a 16:1 multiplexer
- a 1:16 demultiplexer
- two 16:1 multiplexers
- none of the above

**Answer:** a 1:16 demultiplexer

Q.44. Which of the following logic circuits takes data from a single source and distributes it to one of several output lines?

- multiplexer
- demultiplexer
- encoder
- decoder

**Answer:** demultiplexer

Q.45. Which logic device is called a distributor?

- multiplexer
- demultiplexer
- encoder
- decoder

**Answer:** demultiplexer

Q.46. A demultiplexer with 4-bit select input has

- one data input and four data output lines
- one data input and eight data output lines
- one data input and ten data output lines
- one data input and sixteen data output lines

**Answer:** one data input and sixteen data output lines

Q.47. The number of 1:16 demultiplexers required for designing a 4-output 4-variable combinational circuit is

- 16
- 8
- 4
- 1

**Answer:** 1

Q.48. A demultiplexer is used to

- perform arithmetic division
- select data from several inputs and route it to a single
- steer the data from a single input to one of the many outputs
- perform parity checking

**Answer:** steer the data from a single input to one of the many outputs

Q.49. A combinational logic circuit that is used to send data coming from a single source to two or more separate destinations is called

- a decoder
- an encoder
- a multiplexer
- a demultiplexer

**Answer:** a demultiplexer