Digital Electronics

Flip-Flop MCQ

Flip-Flop MCQ

Flip-Flop MCQ, MCQ on Flip-Flop, Multiple Choice Questions on Flip-Flop, Objective Questions on Flip-Flop, Digital Electronics MCQ, Engineering MCQ, J-K Flip-Flop MCQ, S-R Flip-Flop MCQ, D Flip-Flop MCQ, T Flip-Flop MCQ

Logic Gate MCQ

Objective Type Questions

Q.1. A combinational logic circuit

  • must contain flip-flops
  • may contain flip-flops
  • does not contain flip-flops
  • contains latches

Answer: does not contain flip-flops

Q.2. The output of a logic circuit depends upon the sequence in which the input is applied. The circuit

  • is a combinational logic circuit
  • is a sequential logic circuit
  • may be a combinational or sequential logic circuit
  • is none of the above

Answer: is a sequential logic circuit

Q.3. A sequential circuit does not use clock pulses. It is

  • an asynchronous sequential circuit
  • a synchronous sequential circuit
  • a counter
  • a shift register

Answer: an asynchronous sequential circuit

Q.4. In a multi-input sequential circuit only one input is allowed to change at a time. This circuit

  • consists of latches and combinational circuit
  • is a clocked sequential circuit
  • is a serial adder circuit
  • may be a synchronous counter or a shift register

Answer: consists of latches and combinational circuit

Q.5. An asynchronous sequential circuit

  • does not use clock pulses
  • only one input can change at a time
  • consists of combinational circuit and latches
  • meets all the above conditions

Answer: meets all the above conditions

Q.6. The basic memory element in a digital circuit

  • consists of a NAND gate
  • consists of a NOR gate
  • is a flip-flop
  • is a shift register

Answer: is a flip-flop

Q.7. A flip-flop has two outputs which are

  • always 0
  • always 1
  • always complementary
  • all of the above states

Answer: always complementary

Q.8. A flip-flop can be made using

  • basic gates such as AND, OR and NOT
  • NAND gates  
  • NOR gates
  • any of the above 

Answer: any of the above

Q.9. Which of the following flip-flop is used as a latch?

  • J-K flip-flop
  • Master-slave flip-flop
  • T flip-flop
  • D flip-flop

Answer: D flip-flop

Q.10. Which of the following flip-flop is used as a latch?

  • J-K flip-flop
  • Master-slave flip-flop
  • S-R flip-flop
  • T flip-flop

Answer: S-R flip-flop

Q.11. A flip-flop can store

  • one bit of data
  • two bits of data
  • three bits of data
  • any number of bits of data

Answer: one bit of data

Q.12. When an inverter is placed between the inputs of an S-R flip-flop, the resulting flip-flop is a

  • J-K flip-flop
  • Master-slave flip-flop
  • T flip-flop
  • D flip-flop  

Answer: D flip-flop

Q.13. Which of the following input combinations is not allowed in an S-R flip-flop?

  • S = 0, R = 0
  • S = 0, R = 1
  • S = 1, R = 0
  • S = 1, R = 1

Answer: S = 1, R = 1

Q.14. The functional difference between an S-R flip-flop and a J-K flip-flop is that

  • J-K flip-flop is faster than S-R flip-flop
  • J-K flip-flop has a feedback path 
  • J-K flip-flop accepts both inputs 1
  • J-K flip-flop does not require external clock 

Answer: J-K flip-flop accepts both inputs 1

Q.15. When a flip-flop is set, its outputs will be

  • Q=0, \bar{Q}=0
  • Q=1, \bar{Q}=0
  • Q=0, \bar{Q}=1
  • Q=1, \bar{Q}=1

Answer: Q=1, \bar{Q}=0

Q.16. When a flip-flop is reset, its outputs will be

  • Q=0, \bar{Q}=0
  • Q=1, \bar{Q}=1
  • Q=0, \bar{Q}=1
  • Q=1, \bar{Q}=0

Answer: Q=0, \bar{Q}=1

Q.17. For a flip-flop with provisions of preset and clear

  • while presetting, clear is disabled
  • while clearing, preset is disabled
  • above both are true
  • preset and clear operations are performed simultaneously

Answer: above both are true

Q.18. The race around condition occurs in a J-K flip-flop when

  • both inputs are 0
  • both inputs are 1
  • the inputs are complementary
  • any one of the above input combinations is present

Answer: both inputs are 1

Q.19. Master-slave configuration is used in flip-flops to

  • increase its clocking rate
  • reduce power dissipation
  • eliminate race-around condition
  • improve its reliability

Answer: eliminate race-around condition

Q.20. The output Qn of a J-K flip-flop is 1. It changes to 0 when a clock pulse is applied. The inputs Jn and Kn are respectively

  • 0 and X 
  • 1 and X 
  • X and 1 
  • X and 0 

Answer: X and 1 

Q.21. The output Qn of an S-R flip-flop is 1.1t changes to 0 when a clock pulse is applied. The inputs Sn and Rn are respectively

  • X and 1 
  • 0 and 1
  • X and 1
  • 0 and X 

Answer: 0 and 1

Q.22. The output Qn of of a J-K flip-flop is 0. It changes to 1 when a clock pulse is applied. The inputs Jn and Kn are respectively.

  • 1 and X 
  • 0 and X
  • X and 0 
  • X and 1 

Answer: 1 and X 

Q.23. The output Qn of a J-K (or S-R) flip-flop is 0. Its output does not change when a clock pulse is applied. The inputs Jn and Kn (or Sn-Rn) are respectively

  • X and 0 
  • X and 1 
  • 1 and X
  • 0 and X 

Answer: 0 and X 

Q.24. The output Qn of a J-K flip-flop is 1. Its output does not change when a clock pulse is applied. The inputs Jn and Kn are respectively

  • 0X
  • X0
  • 10  
  • 01   

Answer: X0

Q.25. The outputs Q and \bar{Q} of a master-slave S-R flip-flop are connected to its R and S inputs respectively. Its output Q when clock pulses are applied will be

  • permanently 0
  • permanently 1 
  • fixed 0 or 1
  • complementing with every clock pulse

Answer: fixed 0 or 1

Q.26. Flip-flops can be used to make

  • latches
  • bounce-elimination switches
  • registers
  • all of the above

Answer: registers

Q.27. A master-slave flip-flop is triggered

  • when the clock input is at HIGH logic level
  • when the clock input makes a transition from LOW to HIGH
  • when a pulse is applied at the clock input
  • when the clock input is at LOW logic level

Answer: when a pulse is applied at the clock input

Q.28. A J-K M-S flip-flop comprises which of the following configurations?

  • S-R flip-flop followed by an S-R flip-flop
  • S-R flip-flop followed by a J-K flip flop
  • J-K flip flop followed by a J-K flip-flop
  • J-K flip-flop followed by an S-R flip-flop

Answer: J-K flip-flop followed by an S-R flip-flop

Q.29. In a J-K M-S flip-flop, race around is eliminated because of which of the following reasons?

  • output of slave is fed back to the input of master
  • output of master is fed back to the input of slave
  • while the clock drives the master, inverted clock drives the slave
  • J-K flip-flop is followed by S-R flip-flop

Answer: while the clock drives the master, inverted clock drives the slave

Q.30. The toggle mode for a J-K flip-flop is

  • J = 0, K = 0
  • J = 1, K = 0
  • J = 0, K = 1  
  • J = 1, K = 1

Answer: J = 1, K = 1

Q.31. The transparent latch is

  • an S-R flip-flop
  • a D flip-flop
  • a T flip-flop
  • a flip-flop

Answer: a D flip-flop

Q.32. In a master-slave J-K flip-flop, J = K = 1. The state Qn+1 of the flip-flop after the clock pulse will be

  • 0  
  • 1
  • Qn
  • \bar{Q_{n}}

Answer: \bar{Q_{n}}

Q.33. The characteristic equation of a J-K flip-flop is

  • Q_{n+1}=J\bar{Q_{n}}+\bar{K}Q_{n}
  • Q_{n+1}=JQ_{n}+K\bar{Q_{n}}
  • Q_{n+1}=\bar{J}Q_{n}+\bar{K}Q_{n}
  • Q_{n+1}=\bar{J}\bar{Q_{n}}+KQ_{n}

Answer: Q_{n+1}=J\bar{Q_{n}}+\bar{K}Q_{n}

Q.34. The characteristic equation of a D flip-flop is

  • Q_{n+1}=D
  • Q_{n+1}=Q_{n}
  • Q_{n+1}=1
  • Q_{n+1}=\bar{Q_{n}}

Answer: Q_{n+1}=D

Q.35. The characteristic equation of a T flip-flop is

  • Q_{n+1}=\bar{Q_{n}}T+Q_{n}\bar{T}
  • Q_{n+1}=\bar{Q_{n}}\bar{T}+Q_{n}T
  • Q_{n+1}=Q_{n}
  • Q_{n+1}=\bar{Q_{n}}

Answer: Q_{n+1}=\bar{Q_{n}}T+Q_{n}\bar{T}

Q.36. The characteristic equation of an S-R flip-flop is

  • Q_{n+1}=Q_{n}\bar{R}+S
  • Q_{n+1}=\bar{Q_{n}}R+S
  • Q_{n+1}=Q_{n}R+\bar{S}
  • Q_{n+1}=Q_{n}

Answer: Q_{n+1}=Q_{n}\bar{R}+S

Leave a Reply

Your email address will not be published. Required fields are marked *